MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 342

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

S12 Clock, Reset and Power Management Unit (S12CPMU)
Read: Anytime
Write:
342
0x0039
Reset
1. Only possible if PROT=0 (CPMUPROT register) in all MCU Modes (Normal and Special Mode).
2. All bits in Special Mode (if PROT=0).
3. PLLSEL, PSTP, PRE, PCE, RTIOSCSEL: In Normal Mode (if PROT=0).
4. COPOSCSEL0: In Normal Mode (if PROT=0) until CPMUCOP write once has taken place.
5. COPOSCSEL1: In Normal Mode (if PROT=0) until CPMUCOP write once is taken.
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
W
R
If COPOSCSEL0 was cleared by UPOSC=0 (entering Full Stop Mode with COPOSCSEL0=1 or
insufficient OSCCLK quality), then COPOSCSEL0 can be set once again.
COPOSCSEL1 will not be cleared by UPOSC=0 (entering Full Stop Mode with COPOSCSEL1=1
or insufficient OSCCLK quality if OSCCLK is used as clock source for other clock domains: for
instance core clock etc.).
PLLSEL
1
7
After writing CPMUCLKS register, it is strongly recommended to read
back CPMUCLKS register to make sure that write of PLLSEL,
RTIOSCSEL, COPOSCSEL0 and COPOSCSEL1 was successful.
Figure 10-9. S12CPMU Clock Select Register (CPMUCLKS)
PSTP
= Unimplemented or Reserved
0
6
MC9S12G Family Reference Manual,
5
0
0
OSCSEL1
COP
NOTE
0
4
PRE
0
3
Rev.1.01
PCE
2
0
OSCSEL
Freescale Semiconductor
RTI
0
1
OSCSEL0
COP
0
0