MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 289

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

8.3.2.7
There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if
transitions from that state are allowed, depending upon comparator matches or tag hits, and defines the
next state for the state sequencer following a match. The three debug state control registers are located at
the same address in the register address map (0x0027). Each register can be accessed using the COMRV
bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag register
(DBGMFR).
8.3.2.7.1
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the
targeted next state whilst in State1. The matches refer to the match channels of the comparator match
Freescale Semiconductor
Address: 0x0027
Reset
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
W
R
Debug State Control Registers
0
0
7
TBF
Debug State Control Register 1 (DBGSCR1)
0
1
1
Figure 8-9. Debug State Control Register 1 (DBGSCR1)
= Unimplemented or Reserved
0
0
6
Table 8-13. State Control Register Access Encoding
CNT[5:0]
000001
000010
000100
000110
111111
000000
000001
111110
COMRV
..
..
..
MC9S12G Family Reference Manual, Rev.1.01
00
01
10
11
Table 8-12. CNT Decoding Table
5
0
0
ARM bit will be cleared and the tracing session ends.
oldest data has been overwritten by most recent data
Visible State Control Register
64 lines valid; if using Begin trigger alignment,
0
0
4
DBGSCR1
DBGSCR2
DBGSCR3
DBGMFR
SC3
64 lines valid,
63 lines valid
0
Description
3
2 lines valid
4 lines valid
6 lines valid
1 line valid
..
SC2
2
0
S12S Debug Module (S12SDBG)
SC1
0
1
SC0
0
0
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