MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 405

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

12.3.2.3
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0002
Reserved
ETRIGLE
ACMPIE
ETRIGP
ETRIGE
Reset
ASCIE
AFFC
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
6
5
4
3
2
1
0
W
R
ATD Fast Flag Clear All
0 ATD flag clearing done by write 1 to respective CCF[n] flag.
1 Changes all ATD conversion complete flags to a fast clear sequence.
Do not alter this bit from its reset value.It is for Manufacturer use only and can change the ATD behavior.
External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See
Table 12-7
External Trigger Polarity — This bit controls the polarity of the external trigger signal. See
External Trigger Mode Enable — This bit enables the external trigger on one of the AD channels or one of the
ETRIG3-0 inputs as described in
input buffer of this channel is enabled. The external trigger allows to synchronize the start of conversion with
external events.
0 Disable external trigger
1 Enable external trigger
ATD Sequence Complete Interrupt Enable
0 ATD Sequence Complete interrupt requests are disabled.
1 ATD Sequence Complete interrupt will be requested whenever SCF=1 is set.
ATD Compare Interrupt Enable — If automatic compare is enabled for conversion n (CMPE[n]=1 in ATDCMPE
register) this bit enables the compare interrupt. If the CCF[n] flag is set (showing a successful compare for
conversion n), the compare interrupt is triggered.
0 ATD Compare interrupt requests are disabled.
1 For the conversions in a sequence for which automatic compare is enabled (CMPE[n]=1), an ATD Compare
ATD Control Register 2 (ATDCTL2)
0
0
7
For compare disabled (CMPE[n]=0) a read access to the result register will cause the associated CCF[n] flag
to clear automatically.
For compare enabled (CMPE[n]=1) a write access to the result register will cause the associated CCF[n] flag
to clear automatically.
Interrupt will be requested whenever any of the respective CCF flags is set.
for details.
AFFC
= Unimplemented or Reserved
0
6
Figure 12-5. ATD Control Register 2 (ATDCTL2)
MC9S12G Family Reference Manual, Rev.1.01
Table 12-6. ATDCTL2 Field Descriptions
Reserved
5
0
Table
12-5. If the external trigger source is one of the AD channels, the digital
ETRIGLE
0
4
Description
ETRIGP
0
3
Analog-to-Digital Converter (ADC10B12CV2)
ETRIGE
2
0
ASCIE
0
1
Table 12-7
ACMPIE
for details.
0
0
405