MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 371

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Three control bits in the CPMUCOP register allow selection of seven COP time-out periods.
When COP is enabled, the program must write $55 and $AA (in this order) to the CPMUARMCOP
register during the selected time-out period. Once this is done, the COP time-out period is restarted. If the
program fails to do this and the COP times out, a COP reset is generated. Also, if any value other than $55
or $AA is written, a COP reset is generated.
Windowed COP operation is enabled by setting WCOP in the CPMUCOP register. In this mode, writes to
the CPMUARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out
period. A premature write will immediately reset the part.
10.5.3
The on-chip POR circuitry detects when the internal supply VDD drops below an appropriate voltage
level. The POR is deasserted, if the internal supply VDD exceeds an appropriate voltage level (voltage
levels are not specified in this document because this internal supply is not visible on device pins).
10.5.4
The on-chip LVR circuitry detects when one of the supply voltages VDD, VDDF or VDDX drops below
an appropriate voltage level. If LVR is deasserted the MCU is fully operational at the specified maximum
speed. The LVR assert and deassert levels for the supply voltage VDDX are V
specified in the device Reference Manual.
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
COPOSCSEL1
1
0
0
0
0
0
0
0
0
0
0
0
0
Power-On Reset (POR)
Low-Voltage Reset (LVR)
PSTP
x
1
1
1
1
1
0
0
0
0
0
0
0
Table 10-28. COP condition (run, static) in Stop Mode
PCE
1
1
1
0
0
1
1
1
0
0
0
0
x
MC9S12G Family Reference Manual, Rev.1.01
COPOSCSEL0
1
0
0
0
1
1
0
0
1
0
0
0
x
OSCE
x
1
0
1
x
1
1
1
0
1
1
1
0
S12 Clock, Reset and Power Management Unit (S12CPMU)
UPOSC
x
1
x
x
x
1
1
x
0
1
1
0
0
COP counter behavior in Stop Mode
LVRXA
Static (OSCCLK)
Static (OSCCLK)
Satic (OSCCLK)
Static (IRCCLK)
Static (IRCCLK)
Static (IRCCLK)
Static (IRCCLK)
Static (IRCCLK)
Static (IRCCLK)
Static (IRCCLK)
Static (IRCCLK)
Run (OSCCLK)
(clock source)
Run (ACLK)
and V
LVRXD
and are
371