MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 301

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

when the opcode is fetched from the memory, which precedes the instruction execution by an indefinite
number of cycles due to instruction pipelining. For a comparator match of an opcode at an odd address
when TAG = 0, the corresponding even address must be contained in the comparator register. Thus for an
opcode at odd address (n), the comparator register must contain address (n–1).
Once a successful comparator match has occurred, the condition that caused the original match is not
verified again on subsequent matches. Thus if a particular data value is verified at a given address, this
address may not still contain that data value when a subsequent match occurs.
Match[0, 1, 2] map directly to Comparators [A, B, C] respectively, except in range modes (see
Section 8.3.2.4, “Debug Control Register2
the priority section
8.4.2.1
With range comparisons disabled, the match condition is an exact equivalence of address bus with the
value stored in the comparator address registers. Further qualification of the type of access (R/W,
word/byte) and databus contents is possible, depending on comparator channel.
8.4.2.1.1
Comparator C offers only address and direction (R/W) comparison. The exact address is compared, thus
with the comparator address register loaded with address (n) a word access of address (n–1) also accesses
(n) but does not cause a match.
8.4.2.1.2
Comparator B offers address, direction (R/W) and access size (word/byte) comparison. If the SZE bit is
set the access size (word or byte) is compared with the SZ bit value such that only the specified size of
access causes a match. Thus if configured for a byte access of a particular address, a word access covering
the same address does not lead to match.
Assuming the access direction is not qualified (RWE=0), for simplicity, the size access considerations are
shown in
Freescale Semiconductor
1
A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match.
The comparator address register must contain the exact address from the code.
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Word and byte accesses of ADDR[n]
Read and write accesses of ADDR[n]
Condition For Valid Match
Table
Condition For Valid Match
Read accesses of ADDR[n]
Write accesses of ADDR[n]
Single Address Comparator Match
Comparator C
Comparator B
8-32.
(Section 8.4.3.4, “Channel
Table 8-32. Comparator B Access Size Considerations
Table 8-31. Comparator C Access Considerations
MC9S12G Family Reference Manual, Rev.1.01
Comp B Address RWE
ADDR[n]
(DBGC2)). Comparator channel priority rules are described in
Comp C Address RWE
Priorities).
ADDR[n]
1
ADDR[n]
ADDR[n]
1
0
SZE
0
0
1
1
SZ8
RW
X
X
0
1
MOVW #$WORD ADDR[n]
MOVB #$BYTE ADDR[n]
S12S Debug Module (S12SDBG)
LDAA #$BYTE ADDR[n]
STAA #$BYTE ADDR[n]
STAA #$BYTE ADDR[n]
LDAA ADDR[n]
Examples
Examples
301