MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 364

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

S12 Clock, Reset and Power Management Unit (S12CPMU)
The phase detector inside the PLL compares the feedback clock (FBCLK = VCOCLK/(SYNDIV+1)) with
the reference clock (REFCLK = (IRC1M or OSCCLK)/(REFDIV+1)). Correction pulses are generated
based on the phase difference between the two signals. The loop filter alters the DC voltage on the internal
filter capacitor, based on the width and direction of the correction pulse, which leads to a higher or lower
VCO frequency.
The user must select the range of the REFCLK frequency (REFFRQ[1:0] bits) and the range of the
VCOCLK frequency (VCOFRQ[1:0] bits) to ensure that the correct PLL loop bandwidth is set.
The lock detector compares the frequencies of the FBCLK and the REFCLK. Therefore the speed of the
lock detector is directly proportional to the reference clock frequency. The circuit determines the lock
condition based on this comparison.
If PLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and for instance
check the LOCK bit. If interrupt requests are disabled, software can poll the LOCK bit continuously
(during PLL start-up) or at periodic intervals. In either case, only when the LOCK bit is set, the VCOCLK
will have stabilized to the programmed frequency.
10.4.2
An example of startup of clock system from Reset is given in
364
4MHz
f
•
•
•
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
off
osc
The LOCK bit is a read-only indicator of the locked state of the PLL.
The LOCK bit is set when the VCO frequency is within the tolerance ∆
the VCO frequency is out of the tolerance ∆
Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling
the LOCK bit.
REFDIV[3:
Startup from Reset
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0]
1MHz
4MHz
f
REF
REFFRQ[1:0] SYNDIV[5:0]
Table 10-25. Examples of PLL Divider Settings
00
01
MC9S12G Family Reference Manual,
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$05
unl
50MHz
48MHz
.
f
VCO
VCOFRQ[1:0]
Figure
Rev.1.01
01
00
10-30.
POSTDIV
[4:0]
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Lock
and is cleared when
Freescale Semiconductor
50MHz
48MHz
f
PLL
25MHz
24MHz
f
bus