MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 577

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

18.3.2.8
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0005
TXPOL
Reset
AMAP
Field
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
FE
PF
1
0
7
4
W
R
AMAP
Framing Error Flag — FE is set when a logic 0 is accepted as the stop bit. FE bit is set during the same cycle
as the RDRF flag but does not get set in the case of an overrun. FE inhibits further data reception until it is
cleared. Clear FE by reading SCI status register 1 (SCISR1) with FE set and then reading the SCI data register
low (SCIDRL).
0 No framing error
1 Framing error
Parity Error Flag — PF is set when the parity enable bit (PE) is set and the parity of the received data does not
match the parity type bit (PT). PF bit is set during the same cycle as the RDRF flag but does not get set in the
case of an overrun. Clear PF by reading SCI status register 1 (SCISR1), and then reading SCI data register low
(SCIDRL).
0 No parity error
1 Parity error
Alternative Map — This bit controls which registers sharing the same address space are accessible. In the reset
condition the SCI behaves as previous versions. Setting AMAP=1 allows the access to another set of control and
status registers and hides the baud rate and SCI control Register 1.
0 The registers labelled SCIBDH (0x0000),SCIBDL (0x0001), SCICR1 (0x0002) are accessible
1 The registers labelled SCIASR1 (0x0000),SCIACR1 (0x0001), SCIACR2 (0x00002) are accessible
Transmit Polarity — This bit control the polarity of the transmitted data. In NRZ format, a one is represented by
a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA
format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal
polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for
inverted polarity.
0 Normal polarity
1 Inverted polarity
SCI Status Register 2 (SCISR2)
0
7
= Unimplemented or Reserved
0
0
6
Table 18-11. SCISR1 Field Descriptions (continued)
Figure 18-11. SCI Status Register 2 (SCISR2)
MC9S12G Family Reference Manual, Rev.1.01
Table 18-12. SCISR2 Field Descriptions
5
0
0
TXPOL
0
4
Description
Description
RXPOL
0
3
Serial Communication Interface (S12SCIV5)
BRK13
2
0
TXDIR
0
1
RAF
0
0
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