MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 173

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

1
2.4.3.12
2.4.3.13
Freescale Semiconductor
Address 0x001E
Read: Anytime
Write: Anytime
NCLKX2
Reset:
Address 0x001C
NECLK
DIV16
Field
EDIV
Reset
4-0
7
6
5
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
W
R
W
R
No ECLK—Disable ECLK output
This bit controls the availability of a free-running clock on the ECLK pin. This clock has a fixed rate equivalent to the
internal bus clock.
1 ECLK disabled
0 ECLK enabled
No ECLKX2—Disable ECLKX2 output
This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the
internal bus clock.
1 ECLKX2 disabled
0 ECLKX2 enabled
Free-running ECLK predivider—Divide by 16
This bit enables a divide-by-16 stage on the selected EDIV rate.
1 Divider enabled: ECLK rate = EDIV rate divided by 16
0 Divider disabled: ECLK rate = EDIV rate
Free-running ECLK Divider—Configure ECLK rate
These bits determine the rate of the free-running clock on the ECLK pin.
00000 ECLK rate = bus clock rate
00001 ECLK rate = bus clock rate divided by 2
00010 ECLK rate = bus clock rate divided by 3,...
11111 ECLK rate = bus clock rate divided by 32
NECLK
IRQE
ECLK Control Register (ECLKCTL)
IRQ Control Register (IRQCR)
0
7
1
7
IRQEN
NCLKX2
0
6
1
6
Table 2-33. ECLKCTL Register Field Descriptions
Figure 2-13. ECLK Control Register (ECLKCTL)
Figure 2-14. IRQ Control Register (IRQCR)
MC9S12G Family Reference Manual, Rev.1.01
DIV16
0
0
5
0
5
EDIV4
0
0
4
0
4
Description
EDIV3
0
0
3
0
3
EDIV2
2
0
0
0
2
Port Integration Module (S12GPIMV0)
Access: User read/write
Access: User read/write
EDIV1
0
0
1
0
1
EDIV0
0
0
0
0
0
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1