MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 492

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale’s Scalable Controller Area Network (S12MSCANV3)
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
quanta (Tq) clock cycles per bit (as shown in
16.3.2.5
A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition
which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the
CANRIER register.
492
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
1
MSCAN Receiver Flag Register (CANRFLG)
This setting is not valid. Please refer to
TSEG13
Bit Time
1
This setting is not valid. Please refer to
0
0
0
0
1
1
:
TSEG22
0
0
1
1
:
=
TSEG12
(
----------------------------------------------------- -
Prescaler value
0
0
0
0
1
1
:
MC9S12G Family Reference Manual,
f CANCLK
TSEG21
Table 16-10. Time Segment 1 Values
Table 16-9. Time Segment 2 Values
0
0
1
1
:
TSEG11
0
0
1
1
1
1
:
Table 16-9
Table 16-37
TSEG20
)
•
Table 16-37
0
1
0
1
:
(
1
TSEG10
+
and
TimeSegment1
0
1
0
1
0
1
:
for valid settings.
Table
for valid settings.
Rev.1.01
Time Segment 2
2 Tq clock cycles
7 Tq clock cycles
8 Tq clock cycles
1 Tq clock cycle
16-10).
15 Tq clock cycles
16 Tq clock cycles
2 Tq clock cycles
3 Tq clock cycles
Time segment 1
1 Tq clock cycle
4 Tq clock cycles
:
+
TimeSegment2
:
1
Freescale Semiconductor
1
1
1
)
Eqn. 16-1