MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 212

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Port Integration Module (S12GPIMV0)
Both interrupts are capable to wake-up the device from stop mode. Means for glitch filtering are not
provided on these pins.
2.5.4.2
Ports P, J and AD offer pin interrupt capability. The related interrupt enable (PIE) as well as the sensitivity
to rising or falling edges (PPS) can be individually configured on per-pin basis. All bits/pins in a port share
the same interrupt vector. Interrupts can be used with the pins configured as inputs or outputs.
An interrupt is generated when a port interrupt flag (PIF) and its corresponding port interrupt enable (PIE)
are both set. The pin interrupt feature is also capable to wake up the CPU when it is in stop or wait mode.
A digital filter on each pin prevents short pulses from generating an interrupt. A valid edge on an input is
detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active
level. Else the sampling logic is restarted.
In run and wait mode the filters are continuously clocked by the bus clock. Pulses with a duration of t
< n
a pin interrupt.
In stop mode the clock is generated by an RC-oscillator. The minimum pulse length varies over process
conditions, temperature and voltage
assuredly filtered out while pulses with a duration of t
Please refer to the appendix table “Pin Interrupt Characteristics” for pulse length limits.
To maximize current saving the RC oscillator is active only if the following condition is true on any
individual pin:
Sample count <= 4 (at active or passive level) and interrupt enabled (PIE=1) and interrupt flag not set
(PIF=0).
212
P_MASK
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
/f
bus
Pin Interrupts and Wakeup
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
are assuredly filtered out while pulses with a duration of t
Figure 2-65. Interrupt Glitch Filter (here: active low level selected)
MC9S12G Family Reference Manual,
(Figure
t
PULSE
2-65). Pulses with a duration of t
(min) t
uncertain
PULSE
PULSE
(max)
> t
P_PASS
Rev.1.01
guarantee a wakeup event.
PULSE
PULSE
> n
P_PASS
< t
Freescale Semiconductor
P_MASK
/f
bus
guarantee
are
PULSE