MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 34

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MC9S12G

Manufacturer Part Number
MC9S12G
Description
Ignores external trigger. Performs one conversion sequence and stops.
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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Device Overview MC9S12G-Family
1.3.12
1.3.13
1.3.14
Up to 16-channel, 10-bit/12-bit
1. 12-bit resolution only available on S12GA192 and S12GA240 devices.
34
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Bus-off recovery by software intervention or automatically
16-bit time stamp of transmitted/received messages
Up to three SCI modules
Full-duplex or single-wire operation
Standard mark/space non-return-to-zero (NRZ) format
Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths
13-bit baud rate selection
Programmable character length
Programmable polarity for transmitter and receiver
Active edge receive wakeup
Break detect and transmit collision detect supporting LIN 1.3, 2.0, 2.1 and SAE J2602
Up to three SPI modules
Configurable 8- or 16-bit data size
Full-duplex or single-wire bidirectional
Double-buffered transmit and receive
Master or slave mode
MSB-first or LSB-first shifting
Serial clock phase and polarity options
— 3 us conversion time
— 8-/10
— Left or right justified result data
— Wakeup from low power modes on analog comparison > or <= match
— Continuous conversion mode
— External triggers to initiate conversions via GPIO or peripheral outputs such as PWM or TIM
— Multiple channel scans
— Precision fixed voltage reference for ADC conversions
Pins can also be used as digital I/O including wakeup capability
Serial Communication Interface Module (SCI)
Serial Peripheral Interface Module (SPI)
Analog-to-Digital Converter Module (ADC)
1
-bit resolution
1
analog-to-digital converter
MC9S12G Family Reference Manual,
Rev.1.01
Freescale Semiconductor

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