MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 292

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

S12S Debug Module (S12SDBG)
Write: If COMRV[1:0] = 10 and DBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the
targeted next state whilst in State3. The matches refer to the match channels of the comparator match
control logic as depicted in
Register
DBGXCTL control register.
The priorities described in
final state has priority followed by the match on the lower channel number (0,1,2).
8.3.2.7.4
292
Address: 0x0027
SC[3:0]
SC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Reset
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
3–0
W
R
(DBGXCTL). Comparators must be enabled by setting the comparator enable bit in the associated
These bits select the targeted next state whilst in State3, based upon the match event.
0
0
7
Debug Match Flag Register (DBGMFR)
= Unimplemented or Reserved
0
0
6
Table 8-19. State3 — Sequencer Next State Selection
Table 8-35
Figure 8-12. Debug Match Flag Register (DBGMFR)
Figure 8-1
Either Match1 or Match2 to State1....... Match0 to Final State
Either Match1 or Match2 to Final State....... Match0 to State1
Table 8-18. DBGSCR3 Field Descriptions
MC9S12G Family Reference Manual,
Description (Unspecified matches have no effect)
dictate that in the case of simultaneous matches, a match leading to
5
0
0
and described in
Match2 to State2........ Match0 to Final State
Match2 to State2........ Match1 to Final State
Match0 to Final State....... Match1 to State1
Match1 to Final State....... Match2 to State1
Match0 to State2....... Match2 to Final State
Match1 to Final State
Match0 to Final State
0
0
4
Match0 to State1
Match1 to State2
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Section 8.3.2.8.1, “Debug Comparator Control
0
0
3
Rev.1.01
MC2
2
0
Freescale Semiconductor
MC1
0
1
MC0
0
0