MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 367

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

10.4.6
10.4.6.1
This mode is the default mode after System Reset or Power-On Reset.
The Bus clock is based on the PLLCLK, the reference clock for the PLL is internally generated (IRC1M).
The PLL is configured to 50 MHz VCOCLK with POSTDIV set to 0x03. If locked (LOCK=1) this results
in a PLLCLK of 12.5 MHz and a Bus clock of 6.25 MHz. The PLL can be re-configured to other bus
frequencies.
The clock sources for COP and RTI can be based on the internal reference clock generator (IRC1M) or the
RC-Oscillator (ACLK).
10.4.6.2
In this mode, the Bus clock is based on the PLLCLK as well (like PEI). The reference clock for the PLL
is based on the external oscillator.
The clock sources for COP and RTI can be based on the internal reference clock generator or on the
external oscillator clock or the RC-Oscillator (ACLK).
This mode can be entered from default mode PEI by performing the following steps:
Freescale Semiconductor
EXTAL
UPOSC
OSCCLK
PLLSEL
Core
Clock
OSCE
1. Configure the PLL for desired bus frequency.
2. Enable the external oscillator (OSCE bit).
3. Wait for oscillator to start-up and the PLL being locked (LOCK = 1) and (UPOSC =1).
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
System Clock Configurations
PLL Engaged Internal Mode (PEI)
PLL Engaged External Mode (PEE)
enable external Oscillator by writing OSCE bit to one.
based on PLLCLK
crystal/resonator starts oscillating
Figure 10-33. Enabling the External Oscillator
MC9S12G Family Reference Manual, Rev.1.01
select OSCCLK as Core/Bus Clock by writing PLLSEL to zero
UPOSC flag is set upon successful start of oscillation
S12 Clock, Reset and Power Management Unit (S12CPMU)
based on OSCCLK
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