MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 568
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MC9S12G
Manufacturer Part Number
MC9S12G
Description
Ignores external trigger. Performs one conversion sequence and stops.
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12G.pdf
(1160 pages)
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Serial Communication Interface (S12SCIV5)
18.3.1
The memory map for the SCI module is given below in
the address offset. The total address for each register is the sum of the base address for the SCI module and
the address offset for each register.
18.3.2
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Writes to a reserved register locations do not have any effect
and reads of these locations return a zero. Details of register bit and field function follow the register
diagrams, in bit order.
568
SCIASR1
SCIACR1
SCIACR2
SCIBDH
SCIBDL
SCICR1
Register
SCICR2
SCISR1
SCISR2
0x0000
0x0001
0x0002
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Name
1
1
1
2
2
2
Module Memory Map and Register Definition
Register Descriptions
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
RXEDGIF
RXEDGIE
LOOPS
AMAP
TDRE
SBR7
IREN
Bit 7
TIE
0
Figure 18-2. SCI Register Summary (Sheet 1 of 2)
= Unimplemented or Reserved
SCISWAI
TNP1
SBR6
TCIE
TC
6
0
0
0
0
MC9S12G Family Reference Manual,
RSRC
RDRF
SBR5
TNP0
RIE
5
0
0
0
0
TXPOL
SBR12
SBR4
IDLE
ILIE
M
4
0
0
0
Figure
18-2. The address listed for each register is
RXPOL
SBR11
WAKE
SBR3
OR
TE
Rev.1.01
3
0
0
0
BERRM1
BERRV
SBR10
BRK13
SBR2
RE
ILT
NF
2
0
Freescale Semiconductor
BERRM0
BERRIF
BERRIE
TXDIR
SBR9
SBR1
RWU
PE
FE
1
BKDFE
BKDIF
BKDIE
SBR8
SBR0
Bit 0
SBK
RAF
PT
PF
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