MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 613

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale Semiconductor
SPTEF
MODF
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Field
5
4
1
2
1
2
XFRW Bit
XFRW Bit
SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. For
information about clearing this bit and placing data into the transmit data register, please refer to
0 SPI data register not empty.
1 SPI data register empty.
Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is configured as a master and mode
fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in
Section 19.3.2.2, “SPI Control Register 2
register (with MODF set) followed by a write to the SPI control register 1.
0 Mode fault has not occurred.
1 Mode fault has occurred.
Data in SPIDRH is lost in this case.
SPIDRH can be read repeatedly without any effect on SPIF. SPIF Flag is cleared only by the read
of SPIDRL after reading SPISR with SPIF == 1.
Any write to SPIDRH or SPIDRL with SPTEF == 0 is effectively ignored.
Data in SPIDRH is undefined in this case.
0
1
0
1
Read SPISR with SPTEF == 1 then
Read SPISR with SPTEF == 1
Read SPISR with SPIF == 1
Read SPISR with SPIF == 1
Table 19-9. SPTEF Interrupt Flag Clearing Sequence
Table 19-8. SPIF Interrupt Flag Clearing Sequence
MC9S12G Family Reference Manual, Rev.1.01
Table 19-7. SPISR Field Descriptions
SPTEF Interrupt Flag Clearing Sequence
SPIF Interrupt Flag Clearing Sequence
(SPICR2)”. The flag is cleared automatically by a read of the SPI status
then
then
then
Byte Write to SPIDRH
Description
Byte Read SPIDRH
Word Write to (SPIDRH:SPIDRL)
Word Read (SPIDRH:SPIDRL)
Byte Write to SPIDRL
Byte Read SPIDRL
Write to SPIDRL
Read SPIDRL
13
or
or
2
or
or
Byte Write to SPIDRL
Serial Peripheral Interface (S12SPIV5)
Byte Read SPIDRL
1
12
1
1
1
Table
19-9.
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