MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 294

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

S12S Debug Module (S12SDBG)
Read: DBGACTL if COMRV[1:0] = 00
DBGBCTL if COMRV[1:0] = 01
DBGCCTL if COMRV[1:0] = 10
Write: DBGACTL if COMRV[1:0] = 00 and DBG not armed
DBGBCTL if COMRV[1:0] = 01 and DBG not armed
DBGCCTL if COMRV[1:0] = 10 and DBG not armed
294
Address: 0x0028
Address: 0x0028
(Comparators
(Comparators
Reset
Reset
A and B)
A and B)
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Field
BRK
SZE
TAG
W
W
SZ
R
R
7
6
5
4
SZE
0
0
0
7
7
Figure 8-14. Debug Comparator Control Register DBGBCTL (Comparator B)
Figure 8-15. Debug Comparator Control Register DBGCCTL (Comparator C)
Size Comparator Enable Bit — The SZE bit controls whether access size comparison is enabled for the
associated comparator. This bit is ignored if the TAG bit in the same register is set.
0 Word/Byte access size is not used in comparison
1 Word/Byte access size is used in comparison
Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the
associated comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set.
0 Word access size is compared
1 Byte access size is compared
Tag Select— This bit controls whether the comparator match has immediate effect, causing an immediate
state sequencer transition or tag the opcode at the matched address. Tagged opcodes trigger only if they
reach the execution stage of the instruction queue.
0 Allow state sequencer transition immediately on match
1 On match, tag the opcode. If the opcode is about to be executed allow a state sequencer transition
Break— This bit controls whether a comparator match terminates a debug session immediately, independent
of state sequencer state. To generate an immediate breakpoint the module breakpoints must be enabled
using the DBGC1 bit DBGBRK.
0 The debug session termination is dependent upon the state sequencer and trigger conditions.
1 A match on this channel terminates the debug session immediately; breakpoints if active are generated,
tracing, if active, is terminated and the module disarmed.
SZ
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
0
6
6
Table 8-21. DBGXCTL Field Descriptions
MC9S12G Family Reference Manual,
TAG
TAG
5
0
5
0
BRK
BRK
0
0
4
4
Description
RW
RW
0
0
3
3
Rev.1.01
RWE
RWE
2
0
2
0
Freescale Semiconductor
0
0
0
0
1
1
COMPE
COMPE
0
0
0
0