MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 136

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Port Integration Module (S12GPIMV0)
2.3.8
136
PS7
PS6
PS5
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Pins PS7-0
• The SPI0 SS signal is mapped to this pin when used with the SPI function. Depending on the
• 20 TSSOP: The SCI0 TXD signal is mapped to this pin when used with the SCI function. If the SCI0
• 20 TSSOP: The PWM channel 3 signal is mapped to this pin when used with the PWM function. If the
• 32 LQFP: The PWM channel 5 signal is mapped to this pin when used with the PWM function. The
• 64/48/32/20 LQFP: The ECLK signal is mapped to this pin when used with the external clock function.
• The API_EXTCLK signal is mapped to this pin when used with the external clock function. If the
• 20 TSSOP: The ADC ETRIG3 signal is mapped to this pin if PWM channel 3 is routed here. The
• Signal priority:
• The SPI0 SCK signal is mapped to this pin when used with the SPI function. Depending on the
• 20 TSSOP: The TIM channel 3 signal is mapped to this pin when used with the timer function. If the
• 32 LQFP: The TIM channel 5 signal is mapped to this pin when used with the timer function. If the TIM
• Signal priority:
• The SPI0 MOSI signal is mapped to this pin when used with the SPI function. Depending on the
• 20 TSSOP: The TIM channel 2 signal is mapped to this pin when used with the timer function. If the
• 32 LQFP: The TIM channel 4 signal is mapped to this pin when used with the timer function. If the TIM
• Signal priority:
configuration of the enabled SPI0 the I/O state is forced to be input or output.
TXD signal is enabled and routed here the I/O state will depend on the SCI0 configuration.
PWM channel is enabled and routed here the I/O state is forced to output.The enabled PWM channel
forces the I/O state to be an output.
enabled PWM channel forces the I/O state to be an output.
If the ECLK output is enabled the I/O state will be forced to output.
Autonomous Periodic Interrupt clock is enabled and routed here the I/O state is forced to output.
enabled external trigger function has no effect on the I/O state. Refer to
Triggers
20 TSSOP: SS0 > TXD0 > PWM3 > ECLK > API_EXTCLK > GPO
32 LQFP: SS0 > PWM5 > ECLK > API_EXTCLK > GPO
48/64 LQFP: SS0 > ECLK > API_EXTCLK > GPO
100 LQFP: SS0 > API_EXTCLK > GPO
configuration of the enabled SPI0 the I/O state is forced to be input or output.
TIM output compare signal is enabled and routed here the I/O state will be forced to output.
output compare signal is enabled and routed here the I/O state will be forced to output. If the ACMP
timer link is enabled this pin is disconnected from the timer input so that it can still be used as
general-purpose I/O or as timer output. The use case for the ACMP timer link requires the timer input
capture function to be enabled.
20 TSSOP: SCK0 > IOC3 > GPO
32 LQFP: SCK0 > IOC5 > GPO
Others: SCK0 > GPO
configuration of the enabled SPI0 the I/O state is forced to be input or output.
TIM output compare signal is enabled and routed here the I/O state will be forced to output.
output compare signal is enabled and routed here the I/O state will be forced to output.
20 TSSOP: MOSI0 > IOC2 > GPO
32 LQFP: MOSI0 > IOC4 > GPO
Others: MOSI0 > GPO
ETRIG3-0”.
MC9S12G Family Reference Manual,
Table 2-12. Port
S
Pins PS7-0
Rev.1.01
Section 2.6.4, “ADC External
Freescale Semiconductor