MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 588

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Serial Communication Interface (S12SCIV5)
18.4.5.5
This module allows to check for collisions on the LIN bus.
If the bit error circuit is enabled (BERRM[1:0] = 0:1 or = 1:0]), the error detect circuit will compare the
transmitted and the received data stream at a point in time and flag any mismatch. The timing checks run
when transmitter is active (not idle). As soon as a mismatch between the transmitted data and the received
data is detected the following happens:
If the bit error detect feature is disabled, the bit error interrupt flag is cleared.
588
Output Transmit
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This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Input Receive
Bit Error
Shift Register
Shift Register
The next bit transmitted will have a high level (TXPOL = 0) or low level (TXPOL = 1)
The transmission is aborted and the byte in transmit buffer is discarded.
the transmit data register empty and the transmission complete flag will be set
The bit error interrupt flag, BERRIF, will be set.
No further transmissions will take place until the BERRIF is cleared.
LIN Transmit Collision Detection
The RXPOL and TXPOL bit should be set the same when transmission
collision detect feature is enabled, otherwise the bit error interrupt flag may
be set incorrectly.
Receive Shift
Register
Transmit Shift
Register
Compare
Sample
Point
0
1
2
Figure 18-19. Timing Diagram Bit Error Detection
3
Synchronizer Stage
MC9S12G Family Reference Manual,
Figure 18-18. Collision Detect Principle
4
BERRM[1:0] = 0:1
5
Bus Clock
6
7
Compare Sample Points
NOTE
8
9
RXD Pin
TXD Pin
10
11
BERRM[1:0] = 1:1
12
Rev.1.01
13
14
LIN Physical Interface
15
0
Freescale Semiconductor
LIN Bus