MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 541

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
17.3.2.2
The starting polarity of each PWM channel waveform is determined by the associated PPOLx bit in the
PWMPOL register. If the polarity bit is one, the PWM channel output is high at the beginning of the cycle
and then goes low when the duty count is reached. Conversely, if the polarity bit is zero, the output starts
low and then goes high when the duty count is reached.
Freescale Semiconductor
PWME7
PWME6
PWME5
PWME4
PWME3
PWME2
PWME1
PWME0
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Field
unavailable bits return a zero
7
6
5
4
3
2
1
0
Pulse Width Channel 7 Enable
0 Pulse width channel 7 is disabled.
1 Pulse width channel 7 is enabled. The pulse modulated signal becomes available at PWM output bit 7 when
Pulse Width Channel 6 Enable
0 Pulse width channel 6 is disabled.
1 Pulse width channel 6 is enabled. The pulse modulated signal becomes available at PWM output bit 6 when
Pulse Width Channel 5 Enable
0 Pulse width channel 5 is disabled.
1 Pulse width channel 5 is enabled. The pulse modulated signal becomes available at PWM output bit 5 when
Pulse Width Channel 4 Enable
0 Pulse width channel 4 is disabled.
1 Pulse width channel 4 is enabled. The pulse modulated signal becomes available at PWM, output bit 4 when
Pulse Width Channel 3 Enable
0 Pulse width channel 3 is disabled.
1 Pulse width channel 3 is enabled. The pulse modulated signal becomes available at PWM, output bit 3 when
Pulse Width Channel 2 Enable
0 Pulse width channel 2 is disabled.
1 Pulse width channel 2 is enabled. The pulse modulated signal becomes available at PWM, output bit 2 when
Pulse Width Channel 1 Enable
0 Pulse width channel 1 is disabled.
1 Pulse width channel 1 is enabled. The pulse modulated signal becomes available at PWM, output bit 1 when
Pulse Width Channel 0 Enable
0 Pulse width channel 0 is disabled.
1 Pulse width channel 0 is enabled. The pulse modulated signal becomes available at PWM, output bit 0 when
PWM Polarity Register (PWMPOL)
its clock source begins its next cycle.
its clock source begins its next cycle. If CON67=1, then bit has no effect and PWM output line 6 is disabled.
its clock source begins its next cycle.
its clock source begins its next cycle. If CON45 = 1, then bit has no effect and PWM output line 4 is disabled.
its clock source begins its next cycle.
its clock source begins its next cycle. If CON23 = 1, then bit has no effect and PWM output line 2 is disabled.
its clock source begins its next cycle. If CON01 = 1, then bit has no effect and PWM output line 0 is disabled.
its clock source begins its next cycle.
MC9S12G Family Reference Manual, Rev.1.01
Table 17-2. PWME Field Descriptions
Description
Pulse-Width Modulator (S12PWM8B8CV2)
541