MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 344

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

S12 Clock, Reset and Power Management Unit (S12CPMU)
10.3.2.7
This register controls the PLL functionality.
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has
no effect.
344
RTIOSCSEL
0x003A
OSCSEL0
Reset
Field
COP
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
1
0
W
R
RTI Clock Select — RTIOSCSEL selects the clock source to the RTI. Either IRCCLK or OSCCLK. Changing the
RTIOSCSEL bit re-starts the RTI time-out period.
RTIOSCSEL can only be set to 1, if UPOSC=1.
UPOSC= 0 clears the RTIOSCSEL bit.
0 RTI clock source is IRCCLK.
1 RTI clock source is OSCCLK.
COP Clock Select 0 — COPOSCSEL0 and COPOSCSEL1 combined determine the clock source to the COP
(see also
If COPOSCSEL1 = 1, COPOSCSEL0 has no effect regarding clock select and changing the COPOSCSEL0 bit
does not re-start the COP time-out period.
When COPOSCSEL1=0,COPOSCSEL0 selects the clock source to the COP to be either IRCCLK or OSCCLK.
Changing the COPOSCSEL0 bit re-starts the COP time-out period.
COPOSCSEL0 can only be set to 1, if UPOSC=1.
UPOSC= 0 clears the COPOSCSEL0 bit.
0 COP clock source is IRCCLK.
1 COP clock source is OSCCLK
S12CPMU PLL Control Register (CPMUPLL)
0
0
7
Write to this register clears the LOCK and UPOSC status bits.
Table 10-6. COPOSCSEL1, COPOSCSEL0 clock source select description
Table
COPOSCSEL1
Figure 10-10. S12CPMU PLL Control Register (CPMUPLL)
10-6)
0
0
6
0
0
1
Table 10-5. CPMUCLKS Descriptions (continued)
MC9S12G Family Reference Manual,
FM1
5
0
COPOSCSEL0
FM0
NOTE
0
4
0
1
x
Description
0
0
3
Rev.1.01
COP clock source
OSCCLK
IRCCLK
ACLK
2
0
0
Freescale Semiconductor
0
0
1
0
0
0