MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 144

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Port Integration Module (S12GPIMV0)
144
PAD5
PAD4
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
• 32 LQFP: The ACMPO signal of the analog comparator is mapped to this pin when used with the
• 20 TSSOP: The inverting input signal ACMPM of the analog comparator is mapped to this pin when
• The ADC analog input channel signal AN5 and the related digital trigger input are mapped to this pin.
• 20 TSSOP: The SCI0 TXD signal is mapped to this pin. If the SCI0 TXD signal is enabled the I/O state
• 20 TSSOP: The TIM channel 3 signal is mapped to this pin. The TIM forces the I/O state to be an output
• 20 TSSOP: The PWM channel 3 signal is mapped to this pin. If the PWM channel is enabled and
• 20 TSSOP: The ADC ETRIG3 signal is mapped to this pin if PWM channel 3 is routed here. The
• Pin interrupts can be generated if enabled in digital input or output mode.
• Signal priority:
• 20 TSSOP: The non-inverting input signal ACMPP of the analog comparator is mapped to this pin
• The ADC analog input channel signal AN4 and the related digital trigger input are mapped to this pin.
• 20 TSSOP: The SCI0 RXD signal is mapped to this pin. If the SCI0 RXD signal is enabled and routed
• 20 TSSOP: The TIM channel 2 signal is mapped to this pin. The TIM forces the I/O state to be an output
• 20 TSSOP: The PWM channel 2 signal is mapped to this pin. If the PWM channel is enabled and
• 20 TSSOP: The ADC ETRIG2 signal is mapped to this pin if PWM channel 2 is routed here. The
• Pin interrupts can be generated if enabled in digital input or output mode.
• Signal priority:
ACMP function. If the ACMP output is enabled (ACMPC[ACOPE]=1) the I/O state will be forced to
output.
used with the ACMP function. The ACMP function has no effect on the output state. The input buffer
is controlled by the ACDIEN bit.
The ADC function has no effect on the output state. The input buffer is controlled by the related
ATDDIEN bit and the ADC trigger function.
will depend on the SCI0 configuration.
for a timer port associated with an enabled output compare.
routed here the I/O state is forced to output.
enabled external trigger function has no effect on the I/O state. Refer to
Triggers
32 LQFP: ACMPO > GPO
20 TSSOP: TXD0 > IOC3 > PWM3 > GPO
Others: GPO
when used with the ACMP function. The ACMP function has no effect on the output state. The input
buffer is controlled by the ACDIEN bit.
The ADC function has no effect on the output state. The input buffer is controlled by the related
ATDDIEN bit and the ADC trigger function.
here the I/O state will be forced to input.
for a timer port associated with an enabled output compare.
routed here the I/O state is forced to output.
enabled external trigger function has no effect on the I/O state. Refer to
Triggers
20 TSSOP: RXD0 > IOC2 > PWM2 > GPO
Others: GPO
ETRIG3-0”.
ETRIG3-0”.
Table 2-17. Port
MC9S12G Family Reference Manual,
AD
Pins AD7-0 (continued)
Rev.1.01
Section 2.6.4, “ADC External
Section 2.6.4, “ADC External
Freescale Semiconductor