MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 198

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MC9S12G

Manufacturer Part Number
MC9S12G
Description
Ignores external trigger. Performs one conversion sequence and stops.
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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1
1
Port Integration Module (S12GPIMV0)
2.4.3.49
198
Address 0x0270 (G1, G2)
Address 0x0270 (G3)
PT0AD
Read: Anytime
Write: Anytime, write 1 to clear
Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
Field
Field
PIFJ
Reset
Reset
7-0
7-0
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
W
W
R
R
Port J interrupt flag—
If the associated interrupt enable bit is set this flag asserts after a valid active edge was detected on the related pin
(see
polarity select register.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)
0 No active edge occurred
Port AD general-purpose input/output data—Data Register
When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the port data register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the
buffered pin input state is read if the digital input buffers are enabled
PT0AD7
Port AD Data Register (PT0AD)
0
0
0
7
7
Section 2.5.4.2, “Pin Interrupts and
PT0AD6
0
0
0
6
6
Table 2-76. PT0AD Register Field Descriptions
Table 2-75. PIFJ Register Field Descriptions
Figure 2-49. Port AD Data Register (PT0AD)
MC9S12G Family Reference Manual,
PT0AD5
0
0
0
5
5
Wakeup”). This can be a rising or a falling edge based on the state of the
PT0AD4
0
0
0
4
4
Description
Description
PT0AD3
PT0AD3
0
0
3
3
Rev.1.01
(Section 2.3.12, “Pins
PT0AD2
PT0AD2
2
0
2
0
PT0AD1
PT0AD1
Freescale Semiconductor
Access: User read/write
Access: User read/write
AD15-0”).
0
0
1
1
PT0AD0
PT0AD0
0
0
0
0
1
1

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