MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 608

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Serial Peripheral Interface (S12SPIV5)
19.3.2.2
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
608
LSBFE
Reset
CPHA
SSOE
CPOL
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Field
3
2
1
0
W
R
SPI Clock Polarity Bit — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI
modules, the SPI modules must have identical CPOL values. In master mode, a change of this bit will abort a
transmission in progress and force the SPI system into idle state.
0 Active-high clocks selected. In idle state SCK is low.
1 Active-low clocks selected. In idle state SCK is high.
SPI Clock Phase Bit — This bit is used to select the SPI clock format. In master mode, a change of this bit will
abort a transmission in progress and force the SPI system into idle state.
0 Sampling of data occurs at odd edges (1,3,5,...) of the SCK clock.
1 Sampling of data occurs at even edges (2,4,6,...) of the SCK clock.
Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by
asserting the SSOE as shown in
progress and force the SPI system into idle state.
LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and
writes of the data register always have the MSB in the highest bit position. In master mode, a change of this bit
will abort a transmission in progress and force the SPI system into idle state.
0 Data is transferred most significant bit first.
1 Data is transferred least significant bit first.
SPI Control Register 2 (SPICR2)
0
0
7
MODFEN
= Unimplemented or Reserved
0
0
1
1
XFRW
0
6
SSOE
Figure 19-4. SPI Control Register 2 (SPICR2)
0
1
0
1
MC9S12G Family Reference Manual,
Table 19-2. SS Input / Output Selection
Table 19-1. SPICR1 Field Descriptions
5
0
0
Table
SS input with MODF feature
19-2. In master mode, a change of this bit will abort a transmission in
SS is slave select output
MODFEN
SS not used by SPI
SS not used by SPI
Master Mode
0
4
Description
BIDIROE
0
3
Rev.1.01
2
0
0
Slave Mode
SS input
SS input
SS input
SS input
SPISWAI
Freescale Semiconductor
0
1
SPC0
0
0