MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 339

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

10.3.2.3
The POSTDIV register controls the frequency ratio between the VCOCLK and the PLLCLK.
Read: Anytime
Write: Anytime if PLLSEL=1. Else write has no effect.
10.3.2.4
This register provides S12CPMU status bits and flags.
Freescale Semiconductor
0x0036
Reset
If PLL is locked (LOCK=1)
If PLL is not locked (LOCK=0)
If PLL is selected (PLLSEL=1)
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
W
R
S12CPMU Post Divider Register (CPMUPOSTDIV)
S12CPMU Flags Register (CPMUFLG)
0
0
7
Table 10-2. Reference Clock Frequency Selection if OSC_LCP is enabled
Figure 10-6. S12CPMU Post Divider Register (CPMUPOSTDIV)
= Unimplemented or Reserved
0
0
6
REFCLK Frequency Ranges
MC9S12G Family Reference Manual, Rev.1.01
f PLL
f bus
1MHz <= f
f PLL
6MHz < f
2MHz < f
5
0
0
f
REF
=
=
(OSCE=1)
=
f PLL
------------ -
REF
---------------------------------------- -
(
f VCO
---------------
REF
>12MHz
POSTDIV
REF
2
4
<= 12MHz
<= 6MHz
f VCO
<= 2MHz
0
4
+
1
)
S12 Clock, Reset and Power Management Unit (S12CPMU)
0
3
REFFRQ[1:0]
00
01
10
11
POSTDIV[4:0]
2
0
1
1
1
0
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