MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 512

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale’s Scalable Controller Area Network (S12MSCANV3)
16.3.3.2
The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received.
The number of bytes to be transmitted or received is determined by the data length code in the
corresponding DLR register.
Module Base + 0x00X4 to Module Base + 0x00XB
512
Module Base + 0x00X2
Module Base + 0x00X3
DB[7:0]
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
7-0
Reset:
Reset:
Reset:
W
W
R
R
Figure 16-34. Data Segment Registers (DSR0–DSR7) — Extended Identifier Mapping
W
R
Data bits 7-0
Data Segment Registers (DSR0-7)
7
x
7
x
DB7
7
x
Figure 16-32. Identifier Register 2 — Standard Mapping
Figure 16-33. Identifier Register 3 — Standard Mapping
= Unused; always read ‘x’
= Unused; always read ‘x’
Table 16-33. DSR0–DSR7 Register Field Descriptions
x
x
6
6
DB6
6
x
MC9S12G Family Reference Manual,
5
x
5
x
DB5
x
5
x
x
4
4
DB4
Description
4
x
DB3
3
x
3
x
3
x
Rev.1.01
DB2
2
x
2
x
x
2
Freescale Semiconductor
DB1
1
x
1
x
1
x
DB0
0
x
0
x
x
0