MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 299

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

8.3.2.8.8
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG not armed.
8.4
This section provides a complete functional description of the DBG module. If the part is in secure mode,
the DBG module can generate breakpoints but tracing is not possible.
8.4.1
Arming the DBG module by setting ARM in DBGC1 allows triggering the state sequencer, storing of data
in the trace buffer and generation of breakpoints to the CPU. The DBG module is made up of four main
blocks, the comparators, control logic, the state sequencer, and the trace buffer.
The comparators monitor the bus activity of the CPU. All comparators can be configured to monitor
address bus activity. Comparator A can also be configured to monitor databus activity and mask out
individual data bus bits during a compare. Comparators can be configured to use R/W and word/byte
access qualification in the comparison. A match with a comparator register value can initiate a state
sequencer transition to another state (see
a forced match, a state sequencer transition can occur immediately on a successful match of system busses
and comparator registers. Whilst tagging, at a comparator match, the instruction opcode is tagged and only
if the instruction reaches the execution stage of the instruction queue can a state sequencer transition occur.
In the case of a transition to Final State, bus tracing is triggered and/or a breakpoint can be generated.
A state sequencer transition to final state (with associated breakpoint, if enabled) can be initiated by
writing to the TRIG bit in the DBGC1 control register.
The trace buffer is visible through a 2-byte window in the register address map and must be read out using
standard 16-bit word reads.
Freescale Semiconductor
Address: 0x002F
Bits[7:0]
Reset
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
7–0
W
R
Functional Description
S12SDBG Operation
Bit 7
Comparator Data Low Mask Bits — The Comparator data low mask bits control whether the selected
comparator compares the data bus bits [7:0] to the corresponding comparator data compare bits. Data bus
comparisons are only performed if the TAG bit in DBGACTL is clear
0 Do not compare corresponding data bit. Any value of corresponding data bit allows match
1 Compare corresponding data bit
0
7
Debug Comparator Data Low Mask Register (DBGADLM)
Figure 8-22. Debug Comparator Data Low Mask Register (DBGADLM)
Bit 6
0
6
Table 8-30. DBGADLM Field Descriptions
MC9S12G Family Reference Manual, Rev.1.01
Bit 5
5
0
Figure
8-24). Either forced or tagged matches are possible. Using
Bit 4
0
4
Description
Bit 3
0
3
Bit 2
2
0
S12S Debug Module (S12SDBG)
Bit 1
0
1
Bit 0
0
0
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