MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 174

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MC9S12G

Manufacturer Part Number
MC9S12G
Description
Ignores external trigger. Performs one conversion sequence and stops.
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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1
1
Port Integration Module (S12GPIMV0)
2.4.3.14
174
Address 0x001F
IRQEN
Read: Anytime
Write: Only in special mode
Read: Anytime
Write:
IRQE
Field
Reset
7
6
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
IRQE: Once in normal mode, anytime in special mode
IRQEN: Anytime
W
R
Reserved
IRQ select edge sensitive only—
1 IRQ pin configured to respond only to falling edges. Falling edges on the IRQ pin are detected anytime when
0 IRQ pin configured for low level recognition
IRQ enable—
1 IRQ pin is connected to interrupt logic
0 IRQ pin is disconnected from interrupt logic
IRQE=1 and will be cleared only upon a reset or the servicing of the IRQ interrupt.
Reserved Register
x
7
These reserved registers are designed for factory test purposes only and are
not intended for general user access. Writing to these registers when in
special mode can alter the module’s functionality.
If the input is driven to active level (IRQ=0) a write access to set either
IRQCR[IRQEN] and IRQCR[IRQE] to 1 simultaneously or to set
IRQCR[IRQEN] to 1 when IRQCR[IRQE]=1 causes an IRQ interrupt to be
generated if the I-bit is cleared. Refer to
edge-sensitive
Reserved
x
6
Table 2-34. IRQCR Register Field Descriptions
mode”.
MC9S12G Family Reference Manual,
Reserved
Figure 2-15. Reserved Register
5
x
Reserved
NOTE
4
x
Description
Section 2.6.3, “Enabling IRQ
Reserved
x
3
Rev.1.01
Reserved
2
x
Reserved
Freescale Semiconductor
Access: User read/write
1
x
Reserved
0
x
1

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