MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 606

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Serial Peripheral Interface (S12SPIV5)
19.2.2
This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data
when it is configured as master.
19.2.3
This pin is used to output the select signal from the SPI module to another peripheral with which a data
transfer is to take place when it is configured as a master and it is used as an input to receive the slave select
signal when the SPI is configured as slave.
19.2.4
In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.
19.3
This section provides a detailed description of address space and registers used by the SPI.
19.3.1
The memory map for the SPI is given in
base address and an address offset. The base address is defined at the SoC level and the address offset is
defined at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have
no effect.
606
Register
SPIDRH
SPICR1
SPICR2
SPIBR
SPISR
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Name
Memory Map and Register Definition
MISO — Master In/Slave Out Pin
SS — Slave Select Pin
SCK — Serial Clock Pin
Module Memory Map
W
W
W
W
W
R
R
R
R
R
Bit 7
SPIE
SPIF
R15
T15
0
0
= Unimplemented or Reserved
SPPR2
XFRW
SPE
R14
T14
6
0
MC9S12G Family Reference Manual,
Figure 19-2. SPI Register Summary
Figure
SPPR1
SPTEF
SPTIE
R13
T13
5
0
19-2. The address listed for each register is the sum of a
MODFEN
SPPR0
MSTR
MODF
R12
T12
4
BIDIROE
CPOL
R11
T11
Rev.1.01
3
0
0
CPHA
SPR2
R10
T10
2
0
0
Freescale Semiconductor
SPISWAI
SSOE
SPR1
R9
T9
1
0
LSBFE
SPC0
SPR0
Bit 0
R8
T8
0