MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 1006

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Bus Interface
Table 17-14
17-22
Offset 0xDB0, 0xDD0, 0xDF0
Reset
12–15 RTT Read transaction type. Transaction type to run if access is a read. The field description differs subject to
8–11 TRGT Target interface.
Bits Name
W
3–7
R
0
2
EN
0
EN
PF
—
—
describes the fields of the PIWARn registers.
1
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Enable. Enables this address translation
Prefetchable. Indicates that the address space is prefetchable so that prefetching and streaming are
attempted.
0 Not prefetchable
1 Prefetchable
Reserved
0000
0001
0010
0011
0100–1110 Reserved
1111
Note: If this field is set to an I/O port rather than local memory space, attributes for the external I/O
transaction are assigned in an outbound ATMU of that I/O controller.
Note also that it is illegal for a PCI or PCI Express interface to use itself as a target.
the transaction being targeted to I/O interface or to local memory.
Following are the transaction type settings for reads to an I/O interface:
0000–0011 Reserved
0100
0101–1111 Reserved
Following are the transaction type settings for reads to local memory:
0000–0011 Reserved
0100
0101
0110
0111
1000–1111 Reserved
PF
2
3
—
Figure 17-14. PCI Inbound Window Attributes Registers
PCI Interface
PCI Express interface 2
PCI Express interface 1
PCI Express interface 3
Local Memory (DDR SDRAM, Local Bus, SRAM)
Read
Read, don’t snoop local processor
Read, snoop local processor
Reserved
Read, unlock L2 cache line
7
Table 17-14. PIWAR n Field Descriptions
8
TRGT
11 12
RTT
All zeros
Description
15 16
WTT
19 20
—
25 26
Freescale Semiconductor
Access: Read/Write
IWS
31