MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 131

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.2.3.4
Figure 2-4
Table 2-7
2.2.3.5
Figure 2-5
Table 2-8
Freescale Semiconductor
Offset LAWSR0: 0xC10
Reset
Offset LAWBAR0: 0x0_0C08
Reset
Bits
1–7
W
8–31
R
W
Bits
0
0–7
R
LAWSR1: 0xC30
LAWSR2: 0xC50
LAWSR3: 0xC70
LAWSR4: 0xC90
EN
LAWBAR1: 0x0_0C28
LAWBAR2: 0x0_0C48
LAWBAR3: 0x0_0C68
LAWBAR4: 0x0_0C88
0
0
describes LAWBARn fields.
describes LAWARn fields.
BASE_ADDR Identifies the 24 most-significant address bits of the base of local access window n . The
shows the bit fields of the LAWBARn registers.
Figure 2-4. Local Access Window n Base Address Registers (LAWBAR0–LAWBAR7)
shows the bit fields of the LAWARn registers.
1
Name
Local Access Window n Base Address Registers
(LAWBAR0–LAWBAR9)
Local Access Window n Attributes Registers (LAWAR0–LAWAR9)
EN
Name
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure 2-5. Local Access Window n Attributes Registers (LAWAR0–LAWAR7)
—
—
—
0 The local access window n (and all other LAWAR n and LAWBAR n fields) are disabled.
1 The local access window n is enabled and other LAWAR n and LAWBAR n fields combine to
Write reserved, read = 0
Write reserved, read = 0
specified base address should be aligned to the window size, as defined by LAWAR n [SIZE].
identify an address range for this window.
LAWSR5: 0xCB0
LAWSR6: 0xCD0
LAWSR7: 0xCF0
LAWSR8: 0xD10
LAWSR9: 0xD30
LAWBAR5: 0x0_0CA8
LAWBAR6: 0x0_0CC8
LAWBAR7: 0x0_0CE8
LAWBAR8: 0x0_0D08
LAWBAR9: 0x0_0D28
7
7
8
8
Table 2-7. LAWBAR n Field Descriptions
TRGT_ID
Table 2-8. LAWAR n Field Descriptions
11 12
All zeros
All zeros
Description
Description
BASE_ADDR
—
25 26
Access: Read/Write
Access: Read/Write
SIZE
Memory Map
31
31
2-7