MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 308

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

L2 Look-Aside Cache/SRAM
Table 7-28
L2. The transaction types and attributes listed follow MPX bus nomenclature, with the addition of write
allocate (burst write with L2 cache allocation).
pushes triggered by snoops, listed in
7-38
dcbi
dcbf
dcbst
icbi
Clean
IKill
Flush
Write allocate
WWK
32-byte WWF
32-byte WWF atomic
< 32-byte WWF
< 32-byte WWF atomic
Transaction Type
Source of Transaction
lists L2 cache state transitions for all system-initiated (non-core) transactions that change the
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 7-27. State Transitions Due to Core-Initiated Transactions (continued)
Table 7-28. State Transitions Due to System-Initiated Transactions
wt
x
x
x
x
x
x
x
x
x
ci
x
x
1
1
0
1
0
1
0
I,E,M
Initial States
dL1
dL1
iL1
I,E
I,V
L1
gbl
0
0
0
0
0
0
0
0
0
E/EL/T
E/EL/T
E/EL/T
Table
L2
Initial L2
I/
I/
I/
I/E/EL/T
I/E/EL/T
I/E/EL/T
I/E/EL/T
State
EL/T
EL/T
EL/T
EL/T
EL/T
I/E
I/E
EL
I/E
I/E
I/T
EL
I/E
E
T
E
I
7-27.
Hit
No
No
No
L2
Table 7-28
Final States
L1
I
I
I
Final L2
Same
Same
Same
Same
State
E/EL
E/EL
E/EL
EL
EL
EL
E
T
T
T
T
I
I
I
I
I
I
L2
I
I
I
accounts for changes caused by L1 snoop
Allocate and lock regardless of cache external
write (CEW) window
Allocate regardless of CEW window
No allocate if cache-inhibited
Invalidate data, keep lock
Miss in cache external write windows
Hit in cache external write window
Hit in cache external write window
Hit in cache external write window
Hit in cache external write window
Invalidate line
Invalidate data, keep lock
Miss in cache external write windows
Miss in cache external write windows.
Hit in CEW window but need burst data
Hit in cache external write window
Hit in cache external write window. Set lock if
CEW lock attribute set.
Invalidate line
Invalidate data, keep lock
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