MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 1311

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Freescale Semiconductor
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Media-independent interface (MII) sublayer. Sublayer that provides a standard
Medium-dependent interface (MDI) sublayer. Sublayer that defines different connector
Memory access ordering. The specific order in which the processor performs load and
Memory-mapped accesses. Accesses whose addresses use the page or block address
Memory coherency. An aspect of caching in which it is ensured that an accurate view of
Memory consistency. Refers to agreement of levels of memory with respect to a single
Memory management unit (MMU). The functional unit that is capable of translating an
Modified/exclusive/invalid (MEI).
Modified state. MEI state (M) in which one, and only one, caching device has the valid
Most-significant bit (msb). The highest-order bit in an address, registers, data element, or
Most-significant byte (MSB). The highest-order byte in an address, registers, data
NaN. An abbreviation for not a number; a symbolic entity encoded in floating-point
No-op. No-operation. A single-cycle operation that does not affect registers or generate
interface between the MAC layer and the physical layer for 10/100-Mbps
operations. It isolates the MAC layer and the physical layer, enabling the MAC
layer to be used with various implementations of the physical layer.
types for different physical media and PMD devices.
store memory accesses and the order in which those accesses complete.
translation mechanisms provided by the MMU and that occur externally with the
bus protocol defined for memory.
memory is provided to all devices that share system memory.
processor and system memory (for example, on-chip cache, secondary cache, and
system memory).
effective (logical) address
mechanisms, and defining caching methods.
different devices that share a memory system. Note that neither the PowerPC ISA
nor the Power ISA definitions specifies the implementation of an MEI protocol to
ensure cache coherency.
data for that address. The data at this address in external memory is not valid.
instruction encoding.
element, or instruction encoding.
format. There are two types of NaNs—signaling NaNs and quiet NaNs.
bus activity.
to a physical address, providing protection
Cache coherency
protocol used to manage caches on
Glossary-5
Glossary