MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 806

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Table 15-44
15.5.3.5.7
The MIIMCOM register is written by the user.
Table 15-45
15-74
29–31
1–26
0–29
Bits
Bits
27
28
0
Offset eTSEC1:0x2_4524
Reset
W
R
Reset Mgmt Reset management. This bit is cleared by default.
MgmtClk
No Pre
Name
Name
0
—
—
—
describes the fields of the MIIMCFG register.
describes the fields of the MIIMCOM register.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
MII Management Command Register (MIIMCOM)
0 Allow the MII MGMT to perform mgmt read/write cycles if requested via the host interface.
1 Reset the MII MGMT.
Reserved
Preamble suppress. This bit is cleared by default.
0 The MII MGMT performs Mgmt read/write cycles with 32 clocks of preamble.
1 The MII MGMT suppresses preamble generation and reduces the Mgmt cycle from 64 clocks to 32
Reserved
This field determines the clock frequency of the MII management clock (EC_MDC). Its default value is
111.
Note: The eTSEC system clock is derived from (CCB Clock)/2.
000 1/4 of the eTSEC system clock divided by 8
001 1/4 of the eTSEC system clock divided by 8
010 1/6 of the eTSEC system clock divided by 8
011 1/8 of the eTSEC system clock divided by 8
100 1/10 of the eTSEC system clock divided by 8
101 1/14 of the eTSEC system clock divided by 8
110 1/20 of the eTSEC system clock divided by 8
111 1/28 of the eTSEC system clock divided by 8
Reserved
clocks. This is in accordance with IEEE 802.3/22.2.4.4.2.
Figure 15-42. MIIMCOM Register Definition
Table 15-44. MIIMCFG Field Descriptions
Table 15-45. MIIMCOM Descriptions
—
Figure 15-42
All zeros
Description
Description
describes the definition for MIIMCOM.
29
Scan Cycle
Freescale Semiconductor
30
Access: Read/Write
Read Cycle
31