MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 1081
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MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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18.3.5.2.5
The PCI Express inbound window base extended address registers, shown in
most-significant bits of a 64 bit base address.
Table 18-21
18.3.5.2.6
The PCI Express inbound window attributes registers, shown in
translate and other attributes for the translations. 64 Gbytes is the largest window size allowed.
Table 18-22
Freescale Semiconductor
Offset Window 2: 0xDCC
Reset
Offset Window 1: 0xDF0
Reset 0
12–31
0–11
Bits
Bits
0
1
W
W
R
R
Window 3: 0xDAC
Window 2: 0xDD0
Window 3: 0xDB0
EN
0
0
WBEA Window base extended address. This field corresponds to PCI Express address bits [63:44]
Name
Name
EN
—
—
—
0
1
Table 18-22. PCI Express Inbound Window Attributes Registers Field Descriptions
describes the fields of the PCI Express inbound window base extended address registers.
describes the fields of the PCI Express inbound window attributes registers.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure 18-23. PCI Express Inbound Window Attributes Registers (PEXIWAR n )
PCI Express Inbound Window Base Extended Address Registers
(PEXIWBEAR n )
PCI Express Inbound Window Attributes Registers (PEXIWAR n )
Reserved
PF
Enable. This bit controls the enabling/disabling of the translation window.
0 Disable inbound window translation
1 Enable inbound window translation
Reserved
2
1
Figure 18-22. PCI Express Inbound Window Base Extended Address
Table 18-21. PCI Express Inbound Window Base Extended Address
0
3
0 0 0
—
—
0
7
1 1 1
8
TRGT
Register Field Descriptions
Registers (PEXIWBEAR n )
11 12
11 12
1
0 1 0 0
RTT
All zeros
15 16
Description
Description
0
WTT
1 0 0
Figure
19 20
0 0 0 0 0 0
18-23, define the window sizes to
WBEA
—
Figure
PCI Express Interface Controller
25 26
18-22, contain the
1
Access: Read/Write
Access: Read/Write
0
0
IWS
0
1
18-27
31
31
1
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