MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 966
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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DMA Controller
16.3.1.14
The DMA general status register combines all of the status bits from each channel into one register. This
register is read-only.
Table 16-20
16-24
Bits
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
Offset 0x300
Reset
Reset
W
W
R TE0
R TE2
EOLNI0
EOLSI0
EOLNI1
EOLSI1
EOSI0
EOSI1
Name
CH0
CB0
CH1
CB1
TE0
PE0
TE1
PE1
—
—
16
0
describes the fields of the DGSR.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
DMA General Status Register (DGSR)
—
17
—
1
Transfer error, channel 0
0 Normal operation
1 An error condition occurred during the DMA transfer.
Reserved
Channel halted, channel 0
Programming error, channel 0
End-of-links interrupt, channel 0
Channel busy, channel 0
End-of-segment interrupt, channel 0
End-of-lists/direct interrupt, channel 0
Transfer error, channel 1
0 Normal operation
1 An error condition occurred during the DMA transfer.
Reserved
Channel halted, channel 1
Programming error, channel 1
End-of-links interrupt, channel 1
Channel busy, channel 1
End-of-segment interrupt, channel 1
End-of-lists/direct interrupt, channel 1
CH0 PE0 EOLNI0 CB0 EOSI0 EOLSI0 TE1
CH2 PE2 EOLNI2 CB2 EOSI2 EOLSI2 TE3
18
2
Figure 16-22
19
3
Figure 16-22. DMA General Status Register (DGSR)
20
4
Table 16-20. DGSR Field Descriptions
describes the DGSR.
21
5
22
6
23
7
All zeros
All zeros
Description
24
8
—
25
—
9
CH1 PE1 EOLNI1 CB1 EOSI1 EOLSI1
CH3 PE3 EOLNI3 CB3 EOSI3 EOLSI3
10
26
11
27
12
28
13
29
Access: Read Only
Freescale Semiconductor
14
30
15
31
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