MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 277

Manufacturer Part Number

BOARD DEVELOPMENT SYSTEM 8544

Manufacturer

Freescale Semiconductor

PowerQUICC III™r

Processor To Be Evaluated

Data Bus Width

Interface Type

Ethernet, I2C

Operating Supply Voltage

- 0.3 V to + 1.1 V

Leaded Process Compatible

Peak Reflow Compatible (260 C)

Rohs Compliant

For Use With/related Products

For Use With

PPC8544EVTANG - EVAL MPC8544 783FCPBGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

The e500 core connects to the L2 cache and the system interface through the high-speed core complex bus

(CCB). The e500 core and the L2 cache connect to the rest of the integrated device through the e500

coherency module (ECM).

e500 core can simultaneously read 128 bits of data from the L2/SRAM, read 64 bits of data from the

system interface, and write 128 bits of data to the L2/SRAM and/or system interface.

Freescale Semiconductor

(single 128-KB SRAM if L2SIZ=256 KB)

(single 64-KB SRAM if L2SIZ=256 KB)

(single 32-KB SRAM if L2SIZ=256 KB)

(two 128-KB SRAM if L2SIZ=256 KB)

Two quarters of the array are SRAMs

One eighth of the array is an SRAM

Two eighths of the array are SRAM

One quarter of the array is SRAM

Both halves of array are SRAM

One half of array is an SRAM

Connection of the On-Chip Memory to the System

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

Table 7-2. Way Selection for SRAM Accesses (continued)

shows the data connections of the e500 core and L2/SRAM. The

L2 Look-Aside Cache/SRAM