MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 672

Manufacturer Part Number

BOARD DEVELOPMENT SYSTEM 8544

Manufacturer

Freescale Semiconductor

PowerQUICC III™r

Processor To Be Evaluated

Data Bus Width

Interface Type

Ethernet, I2C

Operating Supply Voltage

- 0.3 V to + 1.1 V

Leaded Process Compatible

Peak Reflow Compatible (260 C)

Rohs Compliant

For Use With/related Products

For Use With

PPC8544EVTANG - EVAL MPC8544 783FCPBGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Local Bus Controller

The precharge-to-activate interval parameter, controlled by LSDMR[PRETOACT], defines the earliest

timing for an ACTIVATE or REFRESH command after a PRECHARGE command to the same SDRAM

This parameter, controlled by LSDMR[ACTTORW], defines the earliest timing for a READ/WRITE

command after an ACTIVATE command to the same SDRAM bank.

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

ZZZZZZZZ RAS ADD

Precharge-to-Activate Interval

Activate-to-Read/Write Interval

Figure 14-36. PRETOACT = 2 (2 Clock Cycles)

Figure 14-37. ACTTORW = 2 (2 Clock Cycles)

PRETOACT = 2

Freescale Semiconductor