MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 1076
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
PCI Express Interface Controller
Table 18-17
18.3.5.1.4
The PCI Express outbound window attributes registers, shown in
the window sizes to translate and other attributes for the translations. 64 Gbytes is the largest window size
allowed.
Offset 0xC10
Reset 1
Figure 18-18
Table 18-18
18-22
Offset Window 1: 0xC30
Reset 0
12–31
8–11
Bits
Bits
0–7
1–2
W
0
W
R EN
R
Window 2: 0xC50
Window 3: 0xC70
Window 4: 0xC90
EN
0
0
WBEA Window base extended address. Source address which is the starting point for the outbound translation
Name
Name
Table 18-17. PCI Express Outbound Window Base Address Register n Field Descriptions
WBA
Figure 18-17
EN
—
—
—
—
Figure 18-18. PCI Express Outbound Window Attributes Registers 1–4 (PEXOWAR n )
1
0
0
1
describes the fields of the PCI Express outbound window base address registers.
describes the fields of the PCI Express outbound window attributes registers.
Figure 18-17. PCI Express Outbound Window Attributes Register 0 (PEXOWAR0)
shows the PCI Express outbound window attributes registers 1–4 (PEXOWARn).
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PCI Express Outbound Window Attributes Registers (PEXOWAR n )
2
0
Reserved
window. The window must be aligned based on the size selected in the window size bits. Correspond to
internal platform address bits [0:3]. (where 0 is the msb of the internal platform address)
Window base address. Source address which is the starting point for the outbound translation window. The
window must be aligned based on the size selected in the window size bits. This corresponds to internal
platform address bits [4:23].
2
0
Enable. This bit enables this address translation window. For the default window, this bit is read-only and
always hardwired to 1.
0 Disable outbound translation window
1 Enable outbound translation window
Reserved
ROE NS
ROE NS
0
3
0
3
shows the outbound window attributes register 0 (PEXOWAR0).
0
4
0
4
0 0 0 0
5
0
5
—
0
Table 18-18. PEXOWAR n Field Descriptions
7
0
7
8
0
8
TC
0
TC
0
10 11 12
0
10 11 12
0
—
0
0
0
0
1 0 0
RTT
1 0
RTT
Description
Description
15 16
15 16
0
0
0
WTT
1 0
WTT
1
Figure 18-17
0
19 20
0
19 20
0
0
0 0 0 0 0 0
0 0 0 0
—
—
and
Figure
Freescale Semiconductor
25 26
25 26
0
1
Access: Read/Write
1 0 0 0 1
18-18, define
0 0
Access: Mixed
OWS
OWS
0
1
31
31
1
1
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