MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 646

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Local Bus Controller
Table 14-17
14.3.1.12
The transfer error interrupt enable register (LTEIR), shown in
reporting through the LBC internal interrupt mechanism. Software should clear pending errors in LTESR
before enabling interrupts. After an interrupt has occurred, clearing relevant LTESR error bits negates the
interrupt.
14-26
10–11
13–31
Offset 0x0B8
Reset
Bits
3–4
6–7
12
0
1
2
5
8
9
W
R
BMI — PARI
WARA Write-after-read atomic (WARA) error checking disable
RAWA Read-after-write atomic (RAWA) error checking disable
Name
PARD Parity error checking disabled. Note that uncorrectable read errors may cause the assertion of core_fault_in ,
WPD
0
BMD
CSD
—
—
—
—
—
describes LTEDR fields.
1
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Bus monitor disable
0 Bus monitor is enabled
1 Bus monitor is disabled
Reserved
which causes the core to generate a machine check interrupt, unless it is disabled (by clearing HID1[RFXE]).
If RFXE is zero and this error occurs, PARD must be cleared and LTEIR[PARI] must be set to ensure that an
interrupt is generated. For more information, see
Register 1 (HID1).”
0 Parity error checking is enabled.
1 Parity error checking is disabled.
Reserved
Write protect error checking disable
0 Write protect error checking is enabled.
1 Write protect error checking is disabled.
Reserved
0 WARA error checking is enabled.
1 WARA error checking is disabled.
0 RAWA error checking is enabled.
1 RAWA error checking is disabled.
Reserved
Chip select error checking disable
0 Chip select error checking is enabled.
1 Chip select error checking is disabled.
Reserved
Transfer Error Interrupt Enable Register (LTEIR)
2
3
—
Figure 14-15. Transfer Error Interrupt Enable Register (LTEIR)
4
WPI
5
6
—
Table 14-17. LTEDR Field Descriptions
7
WARA RAWA
8
9
10 11
All zeros
—
Description
Section 6.10.2, “Hardware Implementation-Dependent
CSI
12
13
Figure
14-15, is used to send or block error
—
Freescale Semiconductor
Access: Read/Write
31