MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 956

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DMA Controller
After the current descriptor is processed, the current link descriptor address register is loaded from the next
link descriptor address registers and NLNDARn[EOLND] in the next link descriptor address register is
examined. If EOLND is zero, the DMA controller reads in the new current link descriptor for processing.
If EOLND is set, the last descriptor of the list was just completed. If extended chaining mode is not
enabled, all DMA transfers are complete and the DMA controller halts.
If extended chaining mode is enabled, the DMA controller examines the state of NLSDARn[EOLSD] in
the next list descriptor address register. If EOLSD is clear, the controller loads the contents of the next list
descriptor address register into the current list descriptor address register and reads the new list descriptor
from memory. If EOLSD is set, all DMA transfers are complete and the DMA controller halts.
Figure 16-7
16-14
Offset 0x108
Reset
W
R
0x188
0x208
0x288
0
shows ECLNDARn.
Last link descriptor has been processed
Figure 16-7. Extended Current Link Descriptor Address Registers (ECLNDAR n )
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Extended Chaining
Done — DMA halts
enabled?
N
Is
Figure 16-6. Basic Chaining Mode Flow Chart
Software initializes CLNDAR n with 1st link descriptor
Current link descriptor <- Next link descriptor
Y
Y
1st link descriptor is processed
—
NLNDAR n [EOLND]
Y
All zeros
CLSDAR n <- NLSDAR n
set?
Is
NLSDAR n [EOLSD]
N
set?
Is
N
Freescale Semiconductor
Access: Read/Write
27 28
ECLNDA
31