MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 626
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
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- MPC8544VTALF PDF datasheet #3
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Local Bus Controller
14-6
LSDDQM[0:3]/
LUPWAIT/
LWE[0:3]/
LSDRAS/
LSDCAS/
LSDA10/
LBS[0:3]
LSDWE/
LGPL4/
LPBSE
LGPL0
LGPL1
LGPL2
LGPL3
Signal
LGTA/
LOE/
I/O
I/O GPCM transfer acknowledge/General-purpose line 4/UPM wait/parity byte select
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
O GPCM write enable/SDRAM data mask/UPM byte select. These signals select or validate each byte lane
O SDRAM A10/General-purpose line 0
O SDRAM write enable/General-purpose line 1
O GPCM output enable/SDRAM RAS/General-purpose line 2
O SDRAM CAS/General-purpose line 3
Table 14-2. Local Bus Controller Detailed Signal Descriptions (continued)
of the data bus. For banks with port sizes of 32 bits (as set by BR n [PS]), all four signals are defined. For a
16-bit port size, only bits 0:1 are defined; and for an 8-bit port size, bit 0 is the only defined signal. The
least-significant address bits of each access also determine which byte lanes are considered valid for a
given data transfer.
Meaning
Meaning
Meaning
Meaning
Meaning
Meaning
Timing Assertion/Negation—See
State
State
State
State
State
State
Asserted/Negated—For GPCM operation, LWE[0:3] assert for each byte lane enabled for
Asserted/Negated—For SDRAM accesses, represents address bit 10. When the row address is
Asserted/Negated—Should be connected to the SDRAM device WE input. Acts as the SDRAM
Asserted/Negated—Controls the output buffer of memory when accessing memory/devices in
Asserted/Negated—In SDRAM mode, drives the column address strobe (CAS).
Asserted/Negated—Input in GPCM mode used for transaction termination. It may also be
writing.
For SDRAM operation, LSDDQM[0:3] function as the DQM or data mask signals provided
by JEDEC-compliant SDRAM devices, with one DQM provided per byte lane.
LSDDQM[0:3] are driven high when the LBC wishes to mask a write or disable read data
output from the SDRAM.
LBS[0:3] are programmable byte-select signals in UPM mode. See
Array,”
details regarding the timing of LWE[0:3].
driven, it drives the value of address bit 10. When the column address is driven, it forms
part of the SDRAM command.
One of six general-purpose signals when in UPM mode; it drives a value programmed in
the UPM array.
write enable when accessing SDRAM.
One of six general-purpose signals when in UPM mode, and drives a value programmed
in the UPM array.
GPCM mode. For SDRAM accesses, it is the row address strobe (RAS).
One of six general-purpose lines when in UPM mode; it drives a value programmed in the
UPM array.
One of six general-purpose signals when in UPM mode, and drives a value programmed
in the UPM array.
configured as one of six general-purpose output signals when in UPM mode or as an input
to force the UPM controller to wait for the memory/device.
When configured as LPBSE, it disables any use in GPCM or UPM modes. Because
systems that use read-modify-write parity require an additional memory device, they must
generate a byte-select like a normal data device. ANDing LBS[0:3] through external logic
to achieve the logical function of this byte-select adds a delay to the byte-select path that
can affect memory access timing. The LBC provides this optional byte-select signal that is
an internal AND of the four (active low) byte selects, allowing glueless, faster connection
to RMW-parity devices.
for programming details about LBS[0:3].
Section 14.4.2, “General-Purpose Chip-Select Machine (GPCM),”
Description
Freescale Semiconductor
Section 14.4.4.4, “RAM
for
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