MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 113
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 113 of 1340
- Download datasheet (12Mb)
The DDR controller offers an initialization bypass feature which system designers may use to prevent
re-initialization of main memory during system power-on following abnormal shutdown.
1.3.7
The programmable interrupt controller (PIC) implements the necessary functions to provide a flexible
solution for a general-purpose interrupt control. The interrupt controller unit implements the logic and
programming structures of the OpenPIC architecture. The MPC8544E interrupt controller unit supports its
processor core and provides for 12 external interrupts (with fully nested interrupt delivery), four message
interrupts, internal-logic driven interrupts, and four global high resolution timers. Up to 16 programmable
interrupt priority levels are supported.
The MPC8544E supports reception of interrupt messages from the PCI Express interfaces. The PIC
supports INTx and message shared interrupts (MSI) from the PCI Express interfaces. Four INTx interrupts
are presented as independent PIC interrupt sources. There are 256 individual MSI interrupt sources
supported as eight groups of 32 sources. Each of the eight groups constitutes an independent PIC interrupt
source. Individual interrupt sources have associated with them a vector, priority and destination value.
The interrupt controller unit can be bypassed to allow use of an external interrupt controller.
Inter-processor interrupt (IPI) communication is supported through the external interrupt and core reset
signals of different processor cores on the same device. The four IPIs are only used for self-interrupt in a
single-core device such as the MPC8544E.
1.3.8
The SEC is a modular and scalable security core optimized to process all the algorithms associated with
IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP. Although it is not a protocol processor, the SEC is
designed to perform multi-algorithmic operations (for example, 3DES-HMAC-SHA-1) in a single pass of
the data, and every effort has been made to provide the SEC with the flexibility to perform single-pass
operations for current and emerging security protocols. The version of the SEC used in the MPC8544E is
specifically capable of performing single-pass security cryptographic processing for SSL 3.0, SSL
3.1/TLS 1.0, IPSec, SRTP, and 802.11i.
Freescale Semiconductor
•
This proposal precludes any other simultaneous use of IRQ_OUT.
Software based
The DDR controller also has a software-programmable bit that immediately puts main memory
into self-refresh mode.
It is expected that a critical interrupt routine triggered by an external voltage sense device will have
time to set this bit.
Programmable Interrupt Controller (PIC)
Integrated Security Engine (SEC) for the MPC8544E
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
The features described in this section are only available on the MPC8544E.
The MPC8544 does not include an integrated security engine.
NOTE
Overview
1-15
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