MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 43

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
20.3.2.2
20.3.3
20.3.3.1
20.4
20.4.1
20.4.2
20.4.3
20.4.4
20.4.5
20.4.6
20.4.7
20.4.8
21.1
21.1.1
21.1.2
21.1.3
21.1.3.1
21.1.3.2
21.1.3.3
21.1.3.4
21.2
21.2.1
21.2.2
21.2.2.1
21.2.2.2
21.2.2.3
21.3
21.3.1
21.3.1.1
21.3.1.2
21.3.1.3
21.3.1.4
21.3.1.5
21.3.2
21.3.2.1
21.3.2.2
21.3.2.3
Freescale Semiconductor
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Functional Description................................................................................................. 20-11
Introduction.................................................................................................................... 21-1
External Signal Description ........................................................................................... 21-5
Memory Map/Register Definition ............................................................................... 21-10
Counter Registers..................................................................................................... 20-10
Performance Monitor Interrupt................................................................................ 20-11
Event Counting ........................................................................................................ 20-12
Threshold Events ..................................................................................................... 20-12
Chaining................................................................................................................... 20-13
Triggering ................................................................................................................ 20-13
Burstiness Counting................................................................................................. 20-14
Performance Monitor Events ................................................................................... 20-16
Performance Monitor Examples .............................................................................. 20-28
Overview.................................................................................................................... 21-1
Features...................................................................................................................... 21-3
Modes of Operation ................................................................................................... 21-3
Overview.................................................................................................................... 21-5
Detailed Signal Descriptions ..................................................................................... 21-7
Watchpoint Monitor Register Descriptions ............................................................. 21-11
Trace Buffer Register Descriptions.......................................................................... 21-16
Performance Monitor Local Control Registers (PMLCAn, PMLCBn)................. 20-6
Performance Monitor Counters (PMC0–PMC9)................................................. 20-10
Local Bus (LBC) Debug Mode.............................................................................. 21-4
DDR SDRAM Interface Debug Modes ................................................................. 21-4
Watchpoint Monitor Modes ................................................................................... 21-4
Trace Buffer Modes ............................................................................................... 21-4
Debug Signals—Details......................................................................................... 21-7
Watchpoint Monitor Trigger Signals—Details...................................................... 21-8
Test Signals—Details............................................................................................. 21-8
Watchpoint Monitor Control Registers 0–1 (WMCR0, WMCR1)...................... 21-11
Watchpoint Monitor Address Register (WMAR)................................................ 21-13
Watchpoint Monitor Transaction Mask Register (WMTMR) ............................. 21-14
Watchpoint Monitor Status Register (WMSR) .................................................... 21-16
Trace Buffer Control Registers (TBCR0, TBCR1) ............................................. 21-16
Trace Buffer Address Register (TBAR) .............................................................. 21-19
Trace Buffer Address Mask Register (TBAMR)................................................. 21-19
Watchpoint Monitor Address Mask Register (WMAMR) ................................. 21-14
Debug Features and Watchpoint Facility
Contents
Chapter 21
Title
Number
Page
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