MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 651

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14-22
Freescale Semiconductor
14–15
16–27
28–31
8–13
Bits
2–3
4–5
6–7
0
1
BUFCMDC Additional delay cycles for SDRAM control signals. Defines the number of cycles to be added for each
CLKDIV
Name
EADC
PBYP
ECL
—
—
—
—
describes LCRR fields.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PLL bypass. This bit should be set when using low bus clock frequencies if the PLL is unable to lock.
When in PLL bypass mode, incoming data is captured in the middle of the bus clock cycle.It is
recommended that PLL bypass mode be used at frequencies of 83 MHz or less.
0 The PLL is enabled.
1 The PLL is bypassed.
Reserved
SDRAM command when LSDMR[BUFCMD] = 1.
00 4
01 1
10 2
11 3
Reserved
Extended CAS latency. Determines the extended CAS latency for SDRAM accesses when
LSDMR[CL] = 00.
00 4
01 5
10 6
11 7
Reserved
Additional external address delay cycles. Defines the number of additional cycles for the assertion of
LALE. Note that LALE negates prior to the end of the final local bus clock, as controlled by LBCR[AHD].
00 4
01 1
10 2
11 3
Reserved
System (CCB) clock divider. Sets the frequency ratio between the system (CCB) clock and the memory
bus clock. Only the values shown in the table below are allowed.
Note: It is critical that no transactions are being executed via the local bus while CLKDIV is being
modified. As such, prior to modification, the user must ensure that code is not executing out of the local
bus. Once LCRR[CLKDIV] is written, the register should be read, and then an isync should be executed.
0000–0001 Reserved
0010 4
0011 Reserved
0100 8
0101–0111 Reserved
1000 16
1001–1111 Reserved
Table 14-22. LCRR Field Descriptions
Description
Local Bus Controller
14-31