MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 463
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
11.3.1.4
The I
which can be cleared by software. The MCF and RXAK bits are set at reset; all other I2CSR bits are
cleared on reset.
Table 11-7
Freescale Semiconductor
Bits
0
1
2
3
4
5
2
C status register, shown in
BCSTM Broadcast match
MAAS Addressed as a slave. When the value in I2CDR matches with the calling address, this bit is set. The
Name
SRW
MCF
MBB
MAL
describes the bit settings of the I2CSR.
Offset I
Reset
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
I
Data transfer. When one byte of data is transferred, the bit is cleared. It is set by the falling edge of the 9th
clock of a byte transfer.
0 Byte transfer in progress. MCF is cleared under the following conditions:
1 Byte transfer is completed
processor is interrupted, if I2CCR[MIEN] is set. Next, the processor must check the SRW bit and set
I2CCR[MTX] accordingly. Writing to the I2CCR automatically clears this bit.
0 Not addressed as a slave
1 Addressed as a slave
Bus busy. Indicates the status of the bus. When a START condition is detected, MBB is set. If a STOP
condition is detected, it is cleared.
0 I
1 I
Arbitration lost. Automatically set when the arbitration procedure is lost. Note that the device does not
automatically retry a failed transfer attempt.
0 Arbitration is not lost. Can only be cleared by software
1 Arbitration is lost
0 There has not been a broadcast match.
1 The calling address matches with the broadcast address instead of the programmed slave address. This
Slave read/write. When MAAS is set, SRW indicates the value of the R/W command bit of the calling address,
which is sent from the master.
0 Slave receive, master writing to slave
1 Slave transmit, master reading from slave. This bit is valid only when both of the following conditions are
By checking this bit, the processor can select slave transmit/receive mode according to the command of the
master.
2
W
R
C Status Register (I2CSR)
will also be set if this I
true:
•When I2CDR is read in receive mode or
•When I2CDR is written in transmit mode
2
2
•A complete transfer occurred and no other transfers have been initiated.
•The I
I
2
2
C bus is idle
C bus is busy
C1: 0x00C
C2: 0x10C
MCF
0
1
2
C interface is configured as a slave and has an address match.
MAAS
0
1
Figure 11-5. I
Figure
Table 11-7. I2CSR Field Descriptions
2
C drives an address of all 0s and broadcast mode is enabled.
MBB
11-5, is read only with the exception of the MIF and MAL bits,
0
2
2
C Status Register (I2CSR)
MAL
0
3
Description
BCSTM
0
4
SRW
0
5
MIF
0
6
Access: Mixed
RXAK
1
7
I
2
C Interfaces
11-9
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