MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 799

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

send packets while in back pressure. Again, back pressure is non-standard, yet it can be effective in
reducing the flow of receive packets.
15.5.3.4.5
Control and status to and from the PHY is provided via the two-wire MII management interface described
in IEEE 802.3u. The MII management registers (MII management configuration, command, address,
control, status, and indicator registers) are used to exercise this interface between a host processor and one
or more PHY devices (including the TBI).
The eTSEC MII’s registers provide the ability to perform continuous read cycles (called a scan cycle);
although, scan cycles are not explicitly defined in the standard. If requested (by setting
MIIMCOM[Scan Cycle]), the part performs repetitive read cycles of the PHY status register, for example.
In this way, link characteristics may be monitored more efficiently. The different fields in the MII
management indicator register (scan, not valid and busy) are used to indicate availability of each read of
the scan cycle to the host from MIIMSTAT[PHY scan].
Yet another parameter that can be modified through the MII registers is the length of the MII management
interface preamble. After establishing that a PHY supports preamble suppression, the host may so
configure the eTSEC. While enabled, the length of MII management frames are reduced from 64 clocks
to 32 clocks. This effectively doubles the efficiency of the interface.
15.5.3.5
This section describes the MAC registers.
15.5.3.5.1
MACCFG1 is written by the user.
Offset eTSEC1:0x2_4500; eTSEC3:0x2_5500
Freescale Semiconductor
Reset
Reset
W
W
R
R
Soft_Reset
16
0
MAC Registers
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
—
Controlling PHY Links
MAC Configuration 1 Register (MACCFG1)
1
22
Loop Back
23
Figure 15-36. MACCFG1 Register Definition
Figure 15-36
—
24 25
—
Rx_Flow Tx_Flow
26
describes the definition for the MACCFG1 register.
11
27
All zeros
All zeros
Sync’d Rx EN
Reset Rx MC Reset Tx MC Reset Rx Fun Reset Tx Fun
12
28
Enhanced Three-Speed Ethernet Controllers
Rx_EN
13
29
Sync’d Tx EN
14
30
Access: Mixed
Tx_EN
15
31
15-67