MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 104
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 104 of 1340
- Download datasheet (12Mb)
Overview
1-6
•
Two enhanced three-speed Ethernet controllers (eTSECs)
— Backward compatible with MPC8540/MPC8560 (PowerQUICC III) TSEC
— Three-speed support (10/100/1000 Mbps)
— Two IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers
— Support for two full-duplex FIFO interface modes
— Support for various Ethernet physical interfaces:
— Flexible configuration for multiple PHY interface configurations. See
— TCP/IP acceleration and QoS features available
— Quality of service support:
— Full- and half-duplex Ethernet support (1000 Mbps supports only full duplex):
— Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and IEEE
— VLAN insertion and deletion
— Retransmission following a collision
— CRC generation and verification of inbound/outbound frames
— Programmable Ethernet preamble insertion and extraction of up to 7 bytes
— MAC address recognition:
– 1000 Mbps full-duplex IEEE 802.3 GMII, IEEE 802.3z TBI, RTBI, RGMII, and SGMII
– 10/100 Mbps full and half-duplex IEEE 802.3 MII, IEEE 802.3 RGMII, and RMI
“Enhanced Three-Speed Ethernet Controllers (eTSECs),”
– IP v4 and IP v6 header recognition on receive
– IP v4 header checksum verification and generation
– TCP and UDP checksum verification and generation
– Per-packet configurable acceleration
– Recognition of VLAN, stacked (queue in queue) VLAN, 802.2, PPPoE session, MPLS
– Supported in all FIFO modes
– Transmission from up to eight physical queues
– Reception to up to eight physical queues
– IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or
802.1 virtual local area network (VLAN) tags and priority
– Per-frame VLAN control word or default VLAN for each eTSEC
– Extracted VLAN control word passed to software separately
– Exact match on primary and virtual 48-bit unicast addresses
– VRRP and HSRP support for seamless router fail-over
– Up to 16 exact-match MAC addresses supported
– Broadcast address (accept/reject)
– Hash table match on up to 512 multicast addresses
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
stacks, and ESP/AH IP-security headers
software-programmed PAUSE frame generation and recognition)
for more information.
Section 1.3.13,
Freescale Semiconductor
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