MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 1326
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
LALE (LBC external address latch enable) signal, 14-5,
LBCTL (LBC data buffer control) signal, 14-7, 14-35
LBS[0:3] (LBC UPM byte select) signals, 14-6
LCK[0:2] (LBC clock) signals, 14-8
LCKE (LBC clock enable) signal, 14-7
LCS[0:7] (LBC chip select) signals, 14-5
LCS[5:7] signal select
LCS0 (LBC chip select 0) signal, 14-46
LDP[0:3] (LBC data parity) signals, 14-7, 14-36
LGPL0 (LBC GP line 0) signal, 14-6
LGPL1 (LBC GP line 1) signal, 14-6
LGPL2 (LBC GP line 2) signal, 14-6
LGPL3 (LBC GP line 3) signal, 14-6
LGPL4 (LBC GP line 4) signal, 14-6
LGPL5 (LBC GP line 5) signal, 14-7
LGTA (LBC GPCM transfer acknowledge) signal, 14-6,
Local access windows, 2-3–2-10
Local address map, 1-20
Local bus controller (LBC)
Index-10
global utilities, 19-13
ATMUs, see Address translation and mapping units
configuring local access windows, 2-8
distinguishing local access windows from other mapping
illegal interactions
L2 cache/SRAM window interactions, 2-4
precedence if overlapping among themselves, 2-8
precedence if overlapping with L2 cache/SRAM windows,
registers, 2-7–2-8
see also Local access windows
address and address space checking, 14-33
address mask field—option registers, 14-12
atomic bus operations, 14-35
block diagram, 14-1
boot chip-select operation, 14-46
bus monitor, 14-36
bus turnaround, 14-82
clocks and clock ratios, 14-3
14-33
14-46
between inbound ATMUs and local access windows,
between local access windows and DDR SDRAM chip
by acronym, see Register Index
additional address phases (UPM cycles), 14-83
address following read, 14-82
read data following address, 14-82
read-modify-write cycle (parity), 14-83
clock ratio register (LCRR), 14-30
(ATMUs)
functions, 2-9
2-4
2-10
selects, 2-9
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
configuration
debug mode
DSP hosts (interface to), 14-98
error handling
external access termination (LGTA), 14-46
features, 14-2
functional description, 14-32
general-purpose chip-select machine (GPCM), 14-36
initialization/application information, 14-79–14-112
interrupts
LCS[5:7] signal select, 19-13
LCS[5:7] signal select, 19-35
memory map/register definition, 14-8
memory refresh timer prescaler, 14-20
modes of operation, 14-3
overview, 14-2
parity generation and checking, 14-36, 14-95
performance monitor events, 20-26
peripherals, 14-79
port sizes, 14-83
register descriptions, 14-10
SDRAM interface, 14-47–14-58, 14-85
LBC configuration register (LBCR), 14-29
signal selection (POR), 4-22
source and target ID, 21-4, 21-25
MSC8101 HDI16 interface, 14-98
MSC8102 DSI interface, 14-102
transfer error registers, 14-24–14-29
chip-select and write enable negation timing, 14-40
chip-select assertion timing, 14-39
extended hold time on read accesses, 14-43
GPCM mode
output enable timing, 14-43
programmable wait state configuration, 14-40
relaxed timing, 14-41
timing configuration, 14-37
transfer error interrupt enable register (LTEIR), 14-26
bus clock and clock ratios, 14-3
GPCM mode, registers, 14-13
power-down mode, 14-4
SDRAM mode, registers, 14-16
source ID debug mode, 14-4
UPM mode, registers, 14-15
GPCM timing, 14-81
hierarchy for very high speeds, 14-80
hierarchy on the local bus, 14-80
multiplexed address/data, 14-79
by acronym, see Register Index
address multiplexing, 14-50
basic capabilities, 14-85
commands (Intel PC133 and JEDEC), 14-49
registers, 14-13
Freescale Semiconductor
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