MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 545

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.4.5.5
The RNG interrupt status register tracks the state of possible errors, if those errors are not masked, via the
RNG interrupt control register. The definition of each bit in the interrupt status register is shown in
Figure
Table 12-36
Freescale Semiconductor
Address RNG 0x3_A030
52–55
58–61
59–60
0–50
Bits
Bits
51
56
57
Reset
61
62
63
W
R
12-44.
0
Name
Name
ME
—
IE
—
AE
—
RD
—
—
IE
describes RNG interrupt status register fields.
RNG Interrupt Status Register (RNGISR)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
Internal error
0 No internal error detected
1 Internal error
Reserved
Mode error. Indicates that the host has attempted to write an illegal value to the mode register
0 Valid data
1 Invalid data error
Address error. An illegal read or write address was detected within the RNG address space.
0 No error detected
1 Address error
Reserved
Reserved
Interrupt error. This status bit reflects the state of the ERROR interrupt signal, as sampled by the
controller interrupt status register
0 RNG is not signaling error
1 RNG is signaling error
Reserved
Reset done. This status bit, when high, indicates that the RNG has completed its reset sequence.
0 Reset in progress
1 Reset done
Note: Reset Done resets to 0, but has typically switched to 1 by the time a user checks the register,
Table 12-35. RNG Status Register Field Descriptions (continued)
Table 12-36. RNG Interrupt Status Register Field Descriptions
indicating the EU is ready for operation.
Figure 12-44. RNG Interrupt Status Register
—
(Section 12.6.5.3, “Interrupt Status Register
All zeros
Description
Description
50
51
IE
52
—
55
ME
56
(ISR)”).
Security Engine (SEC) 2.1
AE
57
Access: Read-only
58
—
61
OFU —
62
12-65
63