MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 711
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
During the address phase, the SDRAM address port is set as in
Because the internal bank selects are multiplexed over LA[15:16], LSDMR[BSMA] must be set to 011.
Table 14-40
Table 14-41
programmed according to the specific device’s refresh requirements.
14.5.4.3.6
SDRAMs offer a power-down mode during which the device is not refreshed, and therefore, data is not
maintained. This mode is invoked by driving CKE low, while all internal banks are idle; note that they
must be precharged first.
precharge-all command that is issued by the LBC automatically prior to the self-refresh command.
Freescale Semiconductor
msb of start address
LA[0:14]
shows the address port settings during a READ/WRITE command.
shows the register configuration. PSRT and MPTPR are not shown, but they should be
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 14-40. SDRAM Device Address Port During READ/WRITE Command
Power-Down Mode
LA[0:13]
Table 14-39. SDRAM Device Address Port During Address Phase
—
Internal bank select
Figure 14-75
Register
PSDMR
Table 14-41. Register Settings for 512-Mbyte SDRAMs
OR n
BR n
LA[15:16]
Internal bank select (A[17:18])
ACTTOROW
shows the timing. Note that the figure does not show the
PRETOACT
LA[15:16]
BUFCMD
ROWS
COLS
RFEN
BSMA
RFRC
Field
WRC
XAM
BPD
XBA
MS
AM
OP
BA
PS
CL
BL
V
Don’t care
LA[17]
11_1110_0000_0000_0000_0
011 = SDRAM-local bus
From device data sheet
From device data sheet
From device data sheet
From device data sheet
From device data sheet
11 = 32-bit port size
ext. Base address
Row (A[4:16])
LA[18]
Base address
LA[17:29]
AP
Table
Value
100
100
000
011
11
01
1
1
0
0
14-39.
LA[19:29]
Column
No-connect
LA[30:31]
Local Bus Controller
No-connect
LA[30:31]
14-91
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